Abstract Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 10 4 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10 −18 A µm −1 ). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks.

was 2.6% higher than that of a PVC alone.

Abstract In this paper, a novel reconfigurable logic‐in‐memory built using silicon transistors is proposed. The silicon transistor can be reconfigured as p ‐ or n ‐switchable memory by controlling the polarity of the gate inputs. These electrical characteristics are enabled by utilizing holes or electrons as the majority charge carriers for the positive feedback loop. The reconfigurable logic‐in‐memory functions of the NOT and YES gates with the same cell comprising a silicon transistor and load resistor are demonstrated. Moreover, it is revealed that a two‐input reconfigurable logic‐in‐memory cell, based on two silicon transistors and a load resistor, functions as negative‐AND and OR gates. This novel reconfigurable logic‐in‐memory technology can facilitate the development of next‐generation low‐power and high‐performance computing.

Stateful logic can perform logic operations and simultaneously stores computational results in memory devices. Most stateful logic bases and algorithms have been studied using resistive random‐access memory devices. Herein, stateful full adders consisting of silicon p + –n–p–n + diodes that exhibit switching and memory functions through band modulation are demonstrated. A 1‐bit full adder using ten diodes operates with ten sequential steps of material implication and NOR logic operations, and its energy consumption per operation is 50.4 pJ. Row and column logic operations in a diode crossbar structure enable an N ‐bit full adder algorithm. This study demonstrates the feasibility of achieving fully functional in‐memory computations using silicon diodes.

Physically unclonable functions (PUFs) have emerged as candidates for compact hardware security. In this study, PUFs of reconfigurable feedback field‐effect transistors (R‐FBFETs) with polycrystalline silicon channels are designed for dual entropy sources; the channels have inherent random grain boundary‐induced variabilities. Dual entropy source schemes offer a strategic advantage for resource‐constrained platforms by improving the entropy density, area efficiency, and robustness against cyberattacks within a minimized device footprint. An R‐FBFET operates with two‐channel types in a single device through p‐ and n ‐channel modes controlled by the gate bias; hence, two random bits are extracted from a single device. The uniqueness and high reliability of the dual entropy source PUF are confirmed by an inter‐Hamming distance of 49.13% and an intra‐Hamming distance of 3.47%. The PUF passed the U.S. National Institute of Standards and Technology statistical tests. Moreover, the PUF is used to implement XOR (exclusive‐OR)‐based text encryption and decryption, demonstrating its feasibility for Internet‐of‐things and edge applications.

and the density of states in the a-ITGZO TFT.

Abstract Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 10 4 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10 −18 A µm −1 ). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks.

was 2.6% higher than that of a PVC alone.