Mixed-signal Circuits and Systems Laboratory
서울시립대학교 본교(제1캠퍼스) 첨단융합학부
서민재 교수
Analog-to-Digital Converters (ADC)
SAR ADC
Noise Shaping
발행물
전체 논문
17
11
A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC with Full-Binary Sub-DACs
M.-J. Seo, D.-H. Jin, Y.-D. Kim, S.-I. Hwang, J.-P. Kim, S.-T. Ryu
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
12
A 4.2- mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling
S. N. Kim, W. C. Kim, M.-J. Seo, S. T. Ryu
IEEE Trans. Circuits Syst. II Express Briefs, 2018
13
A 2.7-M Pixels 64-mW CMOS Image Sensor with Multicolumn-Parallel Noise-Shaping SAR ADCs
I.-H. Jang, M.-J. Seo, S.-H. Cho, J.-K. Lee, S.-Y. Baek, S. Kwon, M. Choi, H.-J. Ko, S.-T. Ryu
IEEE J. Solid-State Circuits, 2018
14
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration
S. I. Hwang, J. H. Chung, H. J. Kim, I. H. Jang, M.-J. Seo, S. H. Cho, H. Kang, M. Kwon, S. T. Ryu
IEEE Trans. Electron Devices, 2018
15
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC
D.-J. Chang, W. Kim, M.-J. Seo, H.-K. Hong, S.-T. Ryu
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
16
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
D.-J. Chang, W. Kim, M.-J. Seo, H.-K. Hong, S.-T. Ryu
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
17
ADC
W. Kim, H. Hong, Y. Roh, H. Kang, S. Hwang, D. Jo, D. Chang, M.-J. Seo, S. Ryu
IEEE J. Solid-State Circuits, 2016