발행물
컨퍼런스
IEEE Symposium on VLSI Technology and Circuits (VLSI)
2011
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A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣTDC
A 0.63ps Resolution, 11b Pipeline TDC in 0.13μm CMOS
IEEE International Solid-State Circuits Conference (ISSCC)
A 0.1-fref BW 1GHz Fractional-N PLL with FIR-Embedded Phase-Interpolator-Based Noise Filtering
International SoC Design Conference
Time-Interleaved Sample Clock Generator for Ultrasound Beamformer Application
IEEE Asian Solid-State Circuits Conference (ASSCC)
A High-Gain Wide-Input-Range Time Amplifier with an Open-Loop Architecture and a Gain Equal to Current Bias Ratio