A 12.8–15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation
J. Kim, Y. Jo, H. Park, T. Seong, Y. Lim, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2024
2
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2023
3
A Wide-Lock-In-Range and Low-Jitter 12-14.5-GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop
Y. Lim, J. Kim, Y. Jo, J. Bang, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2022
4
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2020
5
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators
J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2019
6
A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single VCO-Based Edge-Racing Time Quantizer
J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, J. Choi
IEEE Solid-State Circuits Letters (SSC-L), 2019
7
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114
S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2018
8
An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique
Y. Lim, J. Lee, S. Park, Y. Jo, J. Choi
IEEE Journal of Solid-State Circuits (JSSC), 2018
9
A 65nm CMOS 2×2 MIMO Multi-band LTE RF Transceiver for Small Cell Base Stations
K. Lim, S. Lee, Y. Lee, Y. Lim, C. Song, J. Seong, J. Choi, S. Han
IEEE Journal of Solid-State Circuits (JSSC), 2018
10
An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current
Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, J. Choi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017