Design of New Ternary Subtractor and Comparator Without using Ternary to Unary converter

Novel In-memory Computing Circuit using Muller C-element

A simplified, high-speed, Error-tolerant Adder using Zero Padding Method

Low Power Gate Diffusion Input Full Adder using Floating Body

Comparison of Approximate Computing with Sobel Edge Detection

근사 캐리 예측 기반의 오차 허용 가산기의 최근 연구 동향

New Power Efficient Flip-Flop Design Tolerant to Single Node Upset Based on True Single-Phase Clock

Design of Efficient NTT-based Polynomial Multiplier

Multi Look-up Table FPGA Reverse Engineering with Bitstream Extraction and Multiple PIP/PLP Matching

Compact and Power-efficient Sobel Edge Detection with Fully Connected Cube-network-based Stochastic Computing