Scaling Out Chip Interconnect Networks with Implicit Sequence Numbers

PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators

PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup

CacheCraft: Enhancing GPU Performance under Memory Protection through Reconstructed Caching

Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers

Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers

SELCC: Enhancing MLC Reliability and Endurance with Single Cell Error Correction Codes

Unity ECC: Unified Memory Protection Against Bit and Chip Errors

UVMMU: Hardware-Offloaded Page Migration for Heterogeneous Computing

DUO: Exposing On-chip Redundancy to Rank-level ECC for High Reliability