H.264/AVC 를 위한 높은 처리량의 2-D 8 × 8 integer transforms 병렬 구조 설계

Shared hardware, high throughput implementation of 2D 4 × 4 and 8 × 8 integer transform for H.264/AVC high-profile coders

Flexible LDPC Decoder using Stream Data Processing for 802.11n and 802.16e

Artificial neural networks for predicting DGPS carrier phase and pseudorange correction

FPGA를 이용한 Bipolar 드라이버용 PWM 컨트롤러 설계

Code length adaptive LDPC architecture

GPS L1-CA/Galileo 겸용 수신기의 설계

Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding

A Realistic Timing Test Model and Its Applications in High-Speed INterconnect Devices

디지털 시뮬레이션에 의한 CMAC 신경망 직류전동기 속도 제어기 설계