Ferroelectric materials have been intensively investigated for high-performance nonvolatile memory devices in the past decades, owing to their nonvolatile polarization characteristics. Ferroelectric memory devices are expected to exhibit lower power consumption and higher speed than conventional memory devices. However, non-complementary metal-oxide-semiconductor (CMOS) compatibility and degradation due to fatigue of traditional perovskite-based ferroelectric materials have hindered the development of high-density and high-performance ferroelectric memories in the past. The recently developed hafnia-based ferroelectric materials have attracted immense attention in the development of advanced semiconductor devices. Because hafnia is typically used in CMOS processes, it can be directly incorporated into current semiconductor technologies. Additionally, hafnia-based ferroelectrics show high scalability and large coercive fields that are advantageous for high-density memory devices. This review summarizes the recent developments in ferroelectric devices, especially ferroelectric transistors, for next-generation memory and neuromorphic applications. First, the types of ferroelectric memories and their operation mechanisms are reviewed. Then, issues limiting the realization of high-performance ferroelectric transistors and possible solutions are discussed. The experimental demonstration of ferroelectric transistor arrays, including 3D ferroelectric NAND and its operation characteristics, are also reviewed. Finally, challenges and strategies toward the development of next-generation memory and neuromorphic applications based on ferroelectric transistors are outlined.

Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.