A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs

An 8-GS/s 4-bit 340 mW CMOS time interleaved flash analog-to-digital converter

A decision feedback equalizing receiver for the SSTL SDRAM interface with clock-data skew compensation

CMOS sense-amplifier type flip-flop having improved setup/hold margin

Two-phase boosted voltage generator for low-voltage DRAMs

An 8-bit 200 MS/s CMOS folding/interpolating analog-to-digital converter

CMOS digital duty cycle correction circuit for multi-phase clock

A temperature- and supply-insensitive fully on-chip 1 Gb/s CMOS open-drain output driver for high-bandwidth DRAMs

A CMOS high-speed wide-range programmable counter

A compact radix-64 54 x 54 CMOS redundant binary parallel multiplier