A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition

A Single-Loop SS-LMS Algorithm with Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

A 1GHz digital PLL with a 3ps-resolution floating-point number TDC in a 0.18μm CMOS

A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL

An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 mu m CMOS

A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces