발행물

전체 논문

151

51

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL
Hong June Park, Dong-Woo Jee, Yunjae Suh,, Byungsub Kim, Jae-Yoon Sim
IEEE Journal of Solid-State Circuits, 201311

52

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation
Park, Hong-June, Sim, Jae-Yoon, Kim, Byungsub, Seon-Kyoo Lee
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 201309

53

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier
Park, Hong-June, Sim, Jae-Yoon, Kim, Byungsub, Yunjae Suh, Jongmi Lee
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 201303

54

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-mu m CMOS
Park, Hong-June, Sim, Jae-Yoon, Kim, JS, Seo, YH, Suh, Y
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 201302

55

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface
Park, Hong-June, Sim, Jae-Yoon, Kim, Byungsub, Seon-Kyoo Lee
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 201302

56

A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation
Park, Hong-June, Sim, Jae-Yoon, Kim, Byungsub, Jee, DW, Kim, B, Park, HJ, Sim, JY
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 201211

57

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines
Hong June Park, Hae Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim
IEEE Journal of Solid-State Circuits, 201209

58

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping Delta Sigma TDC
Park, Hong-June, Sim, Jae-Yoon, Jee, DW, Seo, YH, Park, HJ, Sim, JY
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 201204

59

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 mu m CMOS
Park, Hong-June, Sim, Jae-Yoon, Seo, YH, Kim, JS, Park, HJ, Sim, JY
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 201203

60

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL
박홍준, 심재윤, Chi, HJ, Choi, YH, Lee, SM, Sim, JY, Park, HJ, Lim, JJ, Kang, PS, Lee, BY, Hong, JC, Lee, HS
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 201110