A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces
Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2023
12
A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Y. Jo, J. Kim, Y. Shin, C. Hwang, H. Park, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2023
13
A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector and Extended Loop Bandwidth
J. Bang, J. Kim, S. Jung, S. Park, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2023
14
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
S. Park, S. Yoo, Y. Shin, J. Lee, J. Choi
IEEE J. Solid-State Circuits (JSSC), 2023
15
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
H. Park, C. Hwang, T. Seong, J. Choi
IEEE J. Solid-State Circuits (JSSC),
16
A Low-Jitter and Low-Fractional Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
C. Hwang, H. Park, Y. Lee, T. Seong, J. Choi
IEEE Journal of Solid-State Circuits, 2022
17
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector
S. Park, S. Choi, S. Yoo, Y. Cho, J. Choi
IEEE Journal of Solid-State Circuits, 2022
18
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked ClockMultiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator
S. Park, S. Yoo, Y. Shin, J. Lee, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2022
19
A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
C. Hwang, H. Park, T. Seong, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2022
20
A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop