A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency
J. Bang, S. Choi, S. Yoo, J. Lee, J. Kim, J. Choi
IEEE European Solid-State Circuits Confer, 2021
22
Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency
H. Park, C. Hwang, T. Seong, Y. Lee, J. Choi
IEEE European Solid-State Circuits Conference (ESSCIRC), 2021
23
A 365fsRMS Jitter and −63dBc-Fractional Spur, 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
H. Park, C. Hwang, T. Seong, Y. Lee, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2021
24
An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS
S. Yoo, S. Park, S. Choi, Y. Cho, H. Yoon, C. Hwang, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2021
25
A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique
J. Kim, Y. Jo, Y. Lim, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2021
26
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim, J. Choi
IEEE Journal of Solid-State Circuits, 2021
27
A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction
Y. Lee, T. Seong, J. Lee, C. Hwang, H. Park, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2020
28
A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N
T. Seong, Y. Lee, C. Hwang, J. Lee, H. Park, K. Lee, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2020
29
A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word
T. Seong, Y. Lee, C. Hwang, J. Lee, H. Park, K. Lee, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2020
30
A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator
Y. Lim, J. Kim, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, J. Choi
IEEE International Solid-State Circuits Conference (ISSCC), 2020