발행물
컨퍼런스
ASP-DAC
,
A large current output boosted voltage generator with non-overlapping clock control for sub-1-v memory applications
IEICE
Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage reduction of sub-1-v-vdd SRAMs
IEEE
A boosted voltage generator for low-voltage DRAM’s
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's
Zigzag Super Cut-off CMOS(ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era