This article proposes Dyamond, a one transistor, one capacitor (1T1C) dynamic random access memory (DRAM) in-memory computing (IMC) accelerator with architecture-to-circuit-level optimizations for high memory density and energy efficiency. The bit column addition (BCA) dataflow introduces output bit-wise accumulation to exploit varying accuracy and energy characteristics across different bit positions. The lower BCA (LBCA) reduces analog-to-digital converter (ADC) operations to enhance energy efficiency with inter-column analog accumulation. The higher BCA (HBCA) improves accuracy through signal enhancement and minimizes energy consumption per ADC readout with signal shift (SS). The design maximizes memory density by dedicating 1T1C cells solely to memory and integrating a compact computation circuit adjacent to the bitline sense amplifier. The memory access power is further reduced with a big-little array structure and a switchable sense amplifier (SWSA), which trades off retention time and energy consumption. Fabricated in 28-nm CMOS, Dyamond integrates 3.54-MB DRAM in a 6.48-mm2 area, achieving 27.2 TOPS/W peak efficiency and outstanding performance in advanced models such as BERT and GPT-2.

This article presents cache-processing-in-memory (PIM), an error correction code (ECC)-compatible embedded dynamic random access memory (eDRAM) PIM-based last-level cache (LLC) with a novel triple-level error correction. Integrating PIM into the cache system causes the existing ECC to become a performance bottleneck, leading to higher latency and decreased computational accuracy. An ECC-compatible eDRAM-PIM enables reliable in-memory computing (IMC) even in less stable DRAM environments while reducing ECC latency for PIM tasks. Cache-PIM proposes three key features: 1) triggered error correction with concurrent error detection (TECCED) reduces cell error correction latency for PIM tasks; 2) adaptive error canceling (AEC) corrects computation errors; and 3) resolution-aware single-cycle voting (RSV) reduces analog-to-digital converter (ADC) readout error. Cache-PIM is fabricated in 28-nm CMOS technology and occupies 0.66-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. A demonstration of ViT-Base on the ImageNet dataset achieves 61% latency reduction compared to the conventional ECC and 77.1% accuracy.