발행물
컨퍼런스
IEEE ESSCIRC
2015
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A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS
IEEE ISSCC
A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and TIming-Skew Calibration in 45nm CMOS
A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique
IEEE CICC
2014
A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout
SID
A Low-Power Fast Readout Circuit using a Dual-Mode Sensing Algorithm for Medium-Size Capacitive Touch Screen Panels