IEEE International Symposium on Integrated Circuits and Systems (ISICAS)
Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC
Oct. 2024
Oct. 2024
IEEE Asian Solid-State Circuits Conference (A-SSCC)
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology
Nov. 2024
Nov. 2024
IEEE Asian Solid-State Circuits Conference (A-SSCC)
A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS
Nov. 2023
Nov. 2023
IEEE Asian Solid-State Circuits Conference (A-SSCC)
A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test
Nov. 2022
Nov. 2022
IEEE Symposium on VLSI Circuits (VLSI-C)
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop
Jun. 2019
Jun. 2019