The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm2), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs.

This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with a thin-film transistor (TFT) embedded flash (eFlash) for a binary/ternary-weight neural network (NN). An eFlash-based synaptic cell capable of programming negative weight values to store binary/ternary weight values (i.e., ±1, 0) and synaptic driving circuits for erase, program, and read operations of synaptic arrays have been proposed. The proposed synaptic driving circuits improve the calculation accuracy of PIM operation by precisely programming the sensing current of the eFlash synaptic cell to the target current (50 nA ± 0.5 nA) using a pulse train. In addition, during PIM operation, the pulse-width modulation (PWM) conversion circuit converts 8-bit input data into one continuous PWM pulse to minimize non-linearity in the synaptic sensing current integration step of the neuron circuit. The prototype chip, including the proposed synaptic driving circuit, PWM conversion circuit, neuron circuit, and digital blocks, is designed and laid out as the accelerator for binary/ternary weighted NN with a size of 324 × 80 × 10 using a 0.35 μm CMOS process. Hybrid bonding technology using bump bonding and wire bonding is used to package the designed CMOS accelerator die and TFT eFlash-based synapse array dies into a single chip package.