The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm2), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs.

This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with a thin-film transistor (TFT) embedded flash (eFlash) for a binary/ternary-weight neural network (NN). An eFlash-based synaptic cell capable of programming negative weight values to store binary/ternary weight values (i.e., ±1, 0) and synaptic driving circuits for erase, program, and read operations of synaptic arrays have been proposed. The proposed synaptic driving circuits improve the calculation accuracy of PIM operation by precisely programming the sensing current of the eFlash synaptic cell to the target current (50 nA ± 0.5 nA) using a pulse train. In addition, during PIM operation, the pulse-width modulation (PWM) conversion circuit converts 8-bit input data into one continuous PWM pulse to minimize non-linearity in the synaptic sensing current integration step of the neuron circuit. The prototype chip, including the proposed synaptic driving circuit, PWM conversion circuit, neuron circuit, and digital blocks, is designed and laid out as the accelerator for binary/ternary weighted NN with a size of 324 × 80 × 10 using a 0.35 μm CMOS process. Hybrid bonding technology using bump bonding and wire bonding is used to package the designed CMOS accelerator die and TFT eFlash-based synapse array dies into a single chip package.

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm2), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs.

This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with a thin-film transistor (TFT) embedded flash (eFlash) for a binary/ternary-weight neural network (NN). An eFlash-based synaptic cell capable of programming negative weight values to store binary/ternary weight values (i.e., ±1, 0) and synaptic driving circuits for erase, program, and read operations of synaptic arrays have been proposed. The proposed synaptic driving circuits improve the calculation accuracy of PIM operation by precisely programming the sensing current of the eFlash synaptic cell to the target current (50 nA ± 0.5 nA) using a pulse train. In addition, during PIM operation, the pulse-width modulation (PWM) conversion circuit converts 8-bit input data into one continuous PWM pulse to minimize non-linearity in the synaptic sensing current integration step of the neuron circuit. The prototype chip, including the proposed synaptic driving circuit, PWM conversion circuit, neuron circuit, and digital blocks, is designed and laid out as the accelerator for binary/ternary weighted NN with a size of 324 × 80 × 10 using a 0.35 μm CMOS process. Hybrid bonding technology using bump bonding and wire bonding is used to package the designed CMOS accelerator die and TFT eFlash-based synapse array dies into a single chip package.

AbstractThis paper presents a lightweight true random number generator (TRNG) using beta radiation that is useful for Internet of Things (IoT) security. In general, a random number generator (RNG) is required for all secure communication devices because random numbers are needed to generate encryption keys. Most RNGs are computer algorithms and use physical noise as their seed. However, it is difficult to obtain physical noise in small IoT devices. Since IoT security functions are required in almost all countries, IoT devices must be equipped with security algorithms that can pass the cryptographic module validation programs of each country. In this regard, it is very cumbersome to embed security algorithms, random number generation algorithms, and even physical noise sources in small IoT devices. Therefore, this paper introduces a lightweight TRNG comprising a thin‐film beta‐radiation source and integrated circuits (ICs). Although the ICs are currently being designed, the IC design was functionally verified at the board level. Our random numbers are output from a verification board and tested according to National Institute of Standards and Technology standards.

In this study, we plan to design an RRAM TEG module for new device verification using an array size of 512 rows x 512 columns using 1T1R active RRAM cells based on MagnaChip $0.18\mu \mathbf{mG}$ process technology. We also plan to use 3.3V devices as select transistors used in TEG modules, which are analog circuits, and ${\mathbf{TaO}}_{\mathbf{x}}/{\mathbf{Ta}}_2{\mathbf{O}}_5$ will be used for new memristor devices.

본 논문에서는 OTP (One-Time Programmable) IP (Intellectual Property)의 개발비용을 절감하고 개발 기간을 단축하기 위해 로직 트랜지스터만 이용한 로직 eFuse (electrical Fuse) OTP IP를 설계하였다. 웨이퍼 테스트 시 테스트 장비에서 FSOURCE 패드를 통해 VDD (=1.5V)보다 높은 2.4V의 외부 프로그램 전압을 eFuse OTP IP에만 공급하므로 eFuse OTP 이외의 다른 IP에는 소자의 신뢰성에 영향을 미치지 않으면서 eFuse OTP cell의 eFuse 링크에 높은 전압을 인가하도록 하였다. 한편 본 논문에서는 128행 $\times$ 8열의 2D (Dimensional) 메모리 어레이에 직접 FSOURCE 전압을 인가하여 eFuse에 인가되는 프로그램 파워를 증가시키면서 디코딩 로직 회로를 저면적으로 구현한 eFuse OTP 셀을 제안하였다. 동부하이텍 $0.11\mu m$ CIS 공정을 이용하여 설계된 1Kb eFuse OTP 메모리 IP의 레이아웃 면적은 $295.595\mu m\times 455.873\mu m$ ($=0.134m{m}^2$)이다. In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595\mu m\times 455.873\mu m$ ($=0.134m{m}^2$).

본 논문에서는 back-gate bias 전압인 VNN (Negative Voltage)을 이용하여 5V의 MV (Medium Voltage) 소자만 이용하여 FN (Fowler-Nordheim) tunneling 방식으로 write하는 MTP cell을 사용하여 512비트 MTP IP를 설계하였다. 사용된 MTP cell은 CG(Control Gate) capacitor, TG(Tunnel Gate) transistor와 select transistor로 구성되어 있다. MTP cell size를 줄이기 위해 TG transistor와 select transistor를 위한 PW(P-Well)과 CG capacitor를 위한 PW 2개만 사용하였으며, DNW(Deep N-Well)은 512bit MTP cell array에 하나만 사용하였다. 512비트 MTP IP 설계에서는 BGR을 이용한 voltage regulator에 의해 regulation된 V1V (=1V)의 전압을 이용하여 VPP와 VNN level detector를 설계하므로 PVT variation에 둔감한 $\pm 8V$의 pumping 전압을 공급할 수 있는 VPP와 VNN 발생회로를 제안하였다. In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of $\pm 8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

본 논문에서는 프로그램 선택 소자는 채널 폭이 큰 NMOS (N-channel MOSFET) 트랜지스터 대신 DNW (Deep N-Well) 안에 형성된 채널 폭이 작은 isolated NMOS 트랜지스터의 body인 PW (P-Well)과 source 노드인 n+ diffusion 영역 사이에 형성된 기생하는 접합 다이오드를 사용하는 NMOS-Diode eFuse OTP (One-Time Programmable) 셀을 제안하였다. 제안된 eFuse OTP 셀은 프로그램 모드에서 NMOS 트랜지스터에 형성되는 기생하는 접합 다이오드를 이용하여 eFuse를 blowing 시킨다. 그리고 읽기 모드에서는 접합 다이오드를 이용하는 것이 아니고 NMOS 트랜지스터를 이용하기 때문에 다이오드의 contact voltage 강하를 제거할 수 있으므로 ‘0’ 데이터에 대한 센싱불량을 제거할 수 있다. 또한 읽기 모드에서 채널 폭이 작은 NMOS 트랜지스터를 이용하여 BL에 전압을 전달하므로 OTP 셀의 blowing되지 않은 eFuse를, 통해 흐르는 읽기 전류를 100㎂ 이내로 억제하여 blowing되지 않은 eFuse가 blowing되는 문제를 해결할 수 있다.