IEEE Asian Solid-State Circuits Conf

A 26.5-37.5 GHz Frequency Divider and a 73-GHz-BW CML Buffer in 0.l3 um

30th Asia and South Pacific Design Automation Conference (ASP-DAC)

Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODEL

2025

Design and Verification Conference in Europe (DVCon Europe)

A UVM Testbench for Checking the Global Convergence of Analog/Mixed-Signal Systems: An Adaptive Decision-Feedback Equalizer Example

2024

Design and Verification Conference US (DVCON)

An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog

2021

IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

Event-Driven Modeling and Simulation of 5G NR-Band RF Transceiver in System Verilog

2021