발행물

전체 논문

104

31

A 20‐GHz Phase‐Locked Loop for 40Gb/s Serializing Transmitter in 0.13‐um CMOS
J. Kim, J.‐K. Kim, B.‐J. Lee, N. Kim, D.‐K. Jeong, W. Kim
IEEE J. Solid‐State Circuits (JSSC), 2006

32

Replica Compensated Linear Regulators for Supply‐Regulated Phase‐Locked Loops
E. Alon, J. Kim, S. Pamarti, K. Chang, M. Horowitz
IEEE J. Solid‐State Circuits (JSSC), 2006

33

A 1.2V‐only 900‐mW 10Gb Ethernet Transceiver and XAUI Interface with Robust VCO Tuning Technique
H.‐R. Lee, M.‐S. Hwang, B.‐J. Lee, Y.‐D. Kim, D. Oh, J. Kim, S.‐H. Lee, D.‐K. Jeong, W. Kim
IEEE J. Solid‐State Circuits (JSSC), 2005

34

Multi‐gigabit‐rate Clock and Data Recovery Based on Blind Oversampling
J. Kim, D.‐K. Jeong
IEEE Communication Magazine, 2003

35

Design of CMOS Adaptive‐bandwidth PLL/DLLs: A General Approach
J. Kim, M. A. Horowitz, G.‐Y. Wei
IEEE Trans. Circuits and Systems II (TCAS-II), 2003

36

Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL
J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas
IEEE J. Solid‐State Circuits (JSSC), 2003

37

Adaptive Supply Serial Links with Sub‐1V Operation and Per-pin Clock Recovery
J. Kim, M. A. Horowitz
IEEE J. Solid‐State Circuits (JSSC), 2002

38

An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation
J. Kim, M. A. Horowitz
IEEE J. Solid‐State Circuits (JSSC), 2002

39

A Variable‐Frequency Parallel I/O Interface with Adaptive Power‐Supply Regulation
G.‐Y. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz
IEEE J. Solid‐State Circuits (JSSC), 2000

40

Adaptive Supply Serial Links with Sub‐1V Operation and Per‐pin Clock Recovery
J. Kim, M. A. Horowitz
IEEE Int’l Solid‐State Circuits Conf (ISSCC), 2002