발행물
컨퍼런스
KCS 2025
2025.02
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An ADC-Free Page Buffer-based CMOS Neuron
Analog Matrix-Vector Multiplication Accelerator using Capacitive Coupling-based Compute-In Memory Technology
Noise Robust Analog Matrix-Vector Multiplication Accelerator Architecture Using Capacitive Coupling Principle
Innovative 3D NAND Structure to Improve Erase Performance and On Current Level
Capacitor-Based ReLU Neuron Circuit with Successive Integration and Rescaling