A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
C.-H. Jan, Peng Bai, S. Biswas, Markus J. Buehler, Zekai Chen, G. Curello, S. Gannavaram, W. Hafez, Jie He, J. Hicks, U. Jalan, N. Lazo, Jiefeng Lin, N. Lindert, Christopher S. Litteken, M. Jones, Myounggon Kang, K. Komeyli, Andrey V. Mezhiba, S. Naskar, Simon Olson, Jang Hyeok Park, Rachael J. Parker, Lirong Pei, I. Post, Nilay Pradhan, C. Prasad, M. B. Prince, J. Rizk, G. Sacks, Hiroyuki Tashiro, D. J. Towner, C. Tsai, Yih Wang, L. Yang, J.-Y. Yeh, J. Yip, K. Mistry
2008