M.-S. Choo, Y. Song, S.-Y. Cho, H.-G. Ko, K. Park, and D.-K. Jeong# "A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response"

M.-S. Choo, K. Park, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong# "A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology"

M. Choi, C.-H. Kye, J. Oh, M.-S. Choo, and D.-K. Jeong# "A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator"

M.-S. Choo, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong# "An optimum injection-timing tracking loop for 5-GHz, 1.13-mW/GHz RO-based injection-locked PLL with 152-fs integrated jitter"

S.-Y. Cho, S. Kim, M.-S. Choo, H.-G. Ko, J. Lee, W. Bae, and D.-K. Jeong# "A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection"

K. Park, J. Lee, K. Lee, M.-S. Choo, S. Jang, S.-H. Chu, S. Kim, and D.-K. Jeong# "A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel"

S. Kim, S. Jang, S.-Y. Cho, M.-S. Choo, G.-S. Jeong, W. Bae, and D.-K. Jeong# "A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique"

High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology

Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC