A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test

Vertical AND Cell Package : AND CiM 을 통한 BNN 운용 방법론

Design of PAM4 Transmitter in 28-nm CMOS Technology

Technology of Channel Equalization at the Receiver in 28nm CMOS

Modeling of DSP-based Receiver and Analysis Data Phase With Stochastic Method

Phase Domain Response 분석을 통한 Injection-Locked Oscillator의 Locking Point 예측

PDR 기반 Injection Point에 따른 Injection-Locked Oscillator의 Locking Time 분석

고속 시리얼 데이터 통신용 채널 등화기 분석