3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

A 2T1C eDRAM-based Compute-In-Memory Macro with 8-to-l Column Multiplexing Scheme for Highly Sparse Binarized Deep Neural Networks

A General Purpose IMC Architecture with ADC-Awared Neural Networks

Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks

Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application

An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery

Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter

Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration