This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to supply noise and reference offset in SE chiplet or die-to-die (D2D) interfaces by using forwarded clock as reference voltages instead of generating them at the RX side. To minimize power consumption for PAM3, a differentially weighted data driver is employed. The proposed XTC-combined FS-puller helps voltage level transition while canceling FEXT from adjacent channels. A decision feedback equalizer (DFE)-embedded sampler enables low-power feedback within 1 UI by eliminating the CML summer structure and directly adding a tap branch to the sampler. A digital on-chip foreground training sequence is used to sequentially train TX per-lane deskew, clock swing level, and RX quadrature error corrector (QEC). Six data lanes, two clock lanes, and one replica lane for testing are implemented using an on-chip 2-mm channel in a 28-nm CMOS technology. In the presence of 200-mVpp 120-MHz sinusoidal supply noise injected at TX, horizontal and vertical eyes with CR-PAM3 are measured as 0.34 UI and 121 mV at BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$<10^{-12}$</tex-math> </inline-formula>, while the conventional PAM3 eye is closed.

This article presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency communication in high-performance computing systems. The proposed low-power global clock distribution not only significantly reduces power consumption across multi-lane RXs but is capable of compensating for the frequency offset without any phase interpolators (PIs). To this end, a fractional divider (FDIV) controlled by CDR is placed close to the global phase locked loop. Moreover, in order to address the suboptimal lock point of conventional baud-rate phase detectors, the proposed CDR employs a background eye-climbing algorithm (ECA), which optimizes the sampling phase and maximizes the vertical eye margin (VEM). Fabricated in a 28 nm CMOS process, the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 32$ </tex-math></inline-formula> Gb/s RX shows a low integrated fractional spur of −40.4 dBc at a 2500 ppm frequency offset. Furthermore, it improves bit-error-rate (BER) performance by increasing the VEM by 26 mV. The entire RX achieves the energy efficiency of 1.8 pJ/bit with the aggregate data rate of 128 Gb/s.