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521
80/20MHz 160mW Multimedia Processor integrated with Embedded DRAM MPEG-4 Accelerator 3D Rendering Engine for Mobile ApplicationsAuthor
Chi-Weon Yoon, Ramchan Woo, Jeonghoon Kook, Se-Joong Lee, Kangmin Lee, Young-Don Bae, In-Cheol Park…
ISSCC 2001, 2001
522
A Comparative Analysis of a DDR-SDRAM, a D-RDRAM and a DDR- FCRAM Using a POPeye SimulatorAuthor
Kangmin Lee, Chi-Weon Yoon, Ramchan Woo, Jeonghoon Kook, Hoi-Jun Yoo
ISCAS 2001, 2001
523
Design and Implementation of CMOS LVDS 2.5Gb/s Transmitter and 1.3Gb/s Receiver for Optical InterconnectionsAuthor
Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-Joo Lee, Hoi-Jun Yoo
ISCAS 2001, 2001
524
A 7.1GB/s Low Power 3D Rendering Engine in 2D Array Embedded Memory Logic CMOSAuthor
Yong-Ha Park, Sun-Ho Han, Jung-Su Kim, Se-Joong Lee, Jeong-Hun Kook, Jae-Won Lim, Ramchan Woo, Hoi-J…
ISSCC 2000, 2000
525
A Novel High Speed Low Power Logic Family : Race LogicAuthor
Se-Joong Lee, Hoi-Jun Yoo
ESSCIRC 2000, 2000
526
A Single Bit line Writng Scheme for Low Power Reconfigurable I/O DRAM MacroAuthor
Jeonghon Kook, Hoi-Jun Yoo
ESSCIRC 2000, 2000
527
One chip - low power Digital-TCXO with Sub-ppm AccuracyAuthor
Se-Joong Lee, Jin-Ho Han, Seung-Ho Hank, Joe-Ho Lee, Jung-Su Kim, Min-Kyu Je, Hoi-Jun Yoo
ISCAS 2000, 2000
528
A 670ps, 64bit Dynamic Low-Power Adder DesignAuthor
Ramchan Woo, Se-Joong Lee, Hoi-Jun Yoo
ISCAS 2000, 2000
529
POPeye: A System Analysis Tool for DRAM Performance MeasurementAuthor
Yon-Kyun Im, Chi-Weon Yoon, Hoi-Jun Yoo, Tae-Sung Jung
ICVC 2000, 2000
530
A 330MHz Low Jitter Fast Locking Direct Skew Compensation DLLAuthor
Joo-Ho Lee, Seon-Ho Han, Hoi-Jun Yoo
ISSCC 2000, 2000
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