발행물

전체 논문

781

61

A 120mW 3D Graphics Rendering Engine with 6Mb Embedded DRAM and 3.2Gbyte/s Runtime Reconfigurable Bus for PDA-Chip
Ramchan Woo, Chi-Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits (JSSC), 2002.10

62

Low-Power Network-on-Chip for High-Performance SoC Design
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
IEEE Transactions on VLSI Systems, 2006.02

63

POPeye: A Simulator for a DRAM Performance Evaluation
Kangmin Lee, Chi-Weon Yoon, Ramchan Woo, Jeonghoon Kook, Hoi-Jun Yoo
Journal of Semiconductor Technology and Science (Special issue on the 2001 Korean Conference on Semiconductors), 2001.06

64

Analysis and Implementation of Practical Cost-Effective Network-on-Chips
Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo
IEEE Design & Test of Computers (Special Issue for NoC), 2005.10

65

Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications
Se-Joong Lee, Kangmin Lee, Seong-Jun Song, Hoi-Jun Yoo
IEEE Transactions on Circuits and Systems II (TCAS), 2005.06

66

Race Logic Architecture (RALA): A Novel Logic Concept Using the Race Scheme of Input Variables
Se-Joong Lee, Hoi-Jun Yoo
IEEE Journal of Solid-State Circuit (JSSC), 2002.02

67

A 0.7fJ/Bit/Search, 2.2ns Search Time, Hybrid-Type TCAM Architecture
Sungdae Choi, Kyomin Sohn, Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits (JSSC), 2005

68

Speculative Loop Pipelining for Hardware Acceleration
Sejong Oh, Tag Gon Kim, Jung Hoon Jho
IEEE Transactions on CAD(TCAD), 2008.03

69

A 155-mW 50-Mvertices/s Graphics Processor With Fixed-Point Programmable Vertex Shader for Mobile Applications
Ju-Ho Sohn, Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ramchan Woo, Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits(JSSC), 2006.05

70

An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC
Byeong-Gyu Nam, Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits(JSSC), 2009.05