발행물

전체 논문

781

721

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth
Park, SJ, Kim, JS, Woo, R, Lee, SJ, Lee, KM, Yang, TH, Jung, JY, Yoo, HJ[Yoo, Hoi-Jun]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 200205

722

Race Logic Architecture (RALA): A novel logic concept using the race scheme of input variables
Lee, SJ, Yoo, HJ[Yoo, Hoi-Jun]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 200202

723

Bit-wise read-compare-write scheme for low power read-modify-write DRAM operation
Park, YH, Choi, S, Yoo, HJ[Yoo, Hoi-Jun]
ELECTRONICS LETTERS, 200201

724

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator, and 3-D rendering engine for mobile applications
Yoon, CW, Woo, R, Kook, J, Lee, SJ, Lee, K, Yoo, HJ[Yoo, Hoi-Jun]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 200111

725

A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system
Park, YH, Han, SH, Lee, JH, Yoo, HJ[Yoo, Hoi-Jun]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 200106

726

Hidden double data transfer scheme for MDL design
Park, SJ, Yoo, HJ[Yoo, Hoi-Jun]
ELECTRONICS LETTERS, 200105

727

Fast lock-on time mixed mode DLL with 10ps jitter
Han, SH, Lee, JH, Yoo, HJ[Yoo, Hoi-Jun]
ELECTRONICS LETTERS, 199909

728

Dual Vt Self-timed CMOS Logic for Low Subthreshold Current Multi-Gigabit Synchronous DRAM
Yoo, HJ[Yoo, Hoi-Jun]
IEEE TANS. CIRCUITS SYST. II, 199809

729

Boosted charge transfer preamplifier for low power Gbit-scale DRAM
Kim, JS, Yoo, HJ[Yoo, Hoi-Jun], Seo, KS
ELECTRONICS LETTERS, 199809

730

A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F(2) cell
Kim, JS, Choi, YS, Yoo, HJ[Yoo, Hoi-Jun], Seo, KS
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 199807