발행물

전체 논문

781

731

A Low Noise Folded Bit-Line Sensing Architecture for Multi-Gb DRAM with Ultra High Density 6F2 Cell
10108688
IEEE J. Solid State Circuits, 199801

732

A study of pipeline architectures for high-speed synchronous DRAMs
Yoo, HJ[Yoo, Hoi-Jun]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 199710

733

An analytical model for the effect of graded gate oxide on the channel electric field in MOSFETs with lightly doped drain structure
Kim, JS, Seo, KS, Yoo, HJ[Yoo, Hoi-Jun]
SOLID-STATE ELECTRONICS, 199704

734

A Study of Pipeline Architectures for High Speed Synchronous DRAM
10108688
IEEE J. Solid State Circuits, 199701

735

A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-giga Bit Synchronous DRAM Application
10108688
IEICE Trans. Electron., 199701

736

CMOS IC와 집적 가능한 비정질 P-i-n 수진기 제작에 관한 연구
10108688
대한광학회 논문지, 199701

737

High speed latchup resistant CMOS data output buffer for submicrometre DRAM application
Yoo, HJ[Yoo, Hoi-Jun]
ELECTRONICS LETTERS, 199611

738

A High Speed Latchup Resistant CMOS Data Output Buffer for Sub-micron DRAM Application
10108688
Electron. Lett., 199601

739

PHASE-LOCKED 2-DIMENSIONAL ARRAYS OF VERTICAL CAVITY SURFACE EMITTING LASERS
YOO, HJ[Yoo, Hoi-Jun], HAYES, JR, PAEK, EG, HARBISON, JP, FLOREZ, LT, Kwon, YS[Kwon, Young-Se]
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 199012

740

Arraymode Analysis of Two-Dimensional Phased Arrays of Vertical Cavity Sutface Emitting Lasers
Yoo, HJ[Yoo, Hoi-Jun], j.r.hayes, e.g.paek, a.scherer, y.s.kwon
IEEE JOURNAL OF QUANTUM ELECTRONICS, 199006