High-Density SRAM Read Access Yield Estimation Methodology

저전압 에스램용 선별 동작 사전 증폭 회로

인공지능 알고리즘 기반 디지털 반도체 회로 성능 예측

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

Bitline Charge-Recycling SRAM Write Assist Circuitry for V-MIN Improvement and Energy Saving

Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis

Power-Gated 9T SRAM Cell for Low-Energy Operation