Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM

Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation

One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM