발행물

전체 논문

16

1

Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks
배준영, 오준석, 이영우, 이명진
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023

2

Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor
박진효, 김수연, 김동영, 김건, 박제원, 유순영, 이영우, 이명진
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022

3

4-Pole Hybrid HVDC Circuit Breaker for Pole-to-Pole (PTP) Fault Protection
김건, 박진효, 김수연, 김태훈, 장한승, 이영우, 이명진
IEEE ACCESS, 2022

4

Reduced-Pin-Count BOST for Test-Cost Reduction
이영광, 이영우, 서성열, 강성호
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022

5

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks
이영우, 임현찬, 이영광, 강성호
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020

6

Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing
서성열, 이영우, 임현찬, 강성호
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2020

7

A low-cost concurrent TSV test architecture with lossless test output compression scheme
Lee, YW (Lee, Young-woo), Lim, H (Lim, Hyunchan), Seo, S (Seo, Sungyoul), Cho, K (Cho, Keewon), Kang, S (Kang, Sungho)
PLOS ONE, 2019

8

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults
Cho, K (Cho, Keewon), Lee, YW (Lee, Young-Woo), Seo, S (Seo, Sungyoul), Kang, S (Kang, Sungho)
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019

9

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost
Choi, I (Choi, Inhyuk), Oh, H (Oh, Hyunggoy), Lee, YW (Lee, Young-Woo), Kang, S (Kang, Sungho)
IEEE TRANSACTIONS ON COMPUTERS, 2018

10

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test
Seo, S (Seo, Sungyoul), Cho, K (Cho, Keewon), Lee, YW (Lee, Young-Woo), Kang, S (Kang, Sungho)
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2018