Limiting the location where electron injection occurs at the cathode interface to a narrower region is the key factor for achieving a highly improved RS performance, which can be achieved by including Ru Nanodots. The development of a memory cell structure truly at the nanoscale with such a limiting factor for the electric-field distribution can solve the non-uniformity issue of future ReRAM.

Abstract The recent progress in the metal‐insulator‐metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO 2 ‐Al 2 O 3 ‐ZrO 2 /TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO 3 , which has a dielectric constant of >100, even at a thickness ∼10 nm. However, there are many technical challenges to overcome before this type of MIM capacitor can be used in mass‐production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the mean time, rutile structure TiO 2 and Al‐doped TiO 2 films might find space to fill the gap between ZAZ and SrTiO 3 MIM capacitors due to their exceptionally high dielectric constant among binary oxides. Achieving a uniform and dense rutile structure is the key technology for the TiO 2 ‐based dielectrics, which depends on having a dense, uniform and smooth RuO 2 layer as bottom electrode. Although the Ru (and RuO 2 ) layers grown by ALD using metal‐organic precursors are promising, recent technological breakthroughs using the RuO 4 precursor made a thin, uniform, and denser Ru and RuO 2 layer on a TiN electrode. A minimum equivalent oxide thickness as small as 0.45 nm with a low enough leakage current was confirmed, even in laboratory scale experiments. The bulk dielectric constant of ALD SrTiO 3 films, grown at 370 °C, was ∼150 even with thicknesses ≤15 nm. The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD SrTiO 3 film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high capacitor density and three‐dimensional structures are necessary.

Limiting the location where electron injection occurs at the cathode interface to a narrower region is the key factor for achieving a highly improved RS performance, which can be achieved by including Ru Nanodots. The development of a memory cell structure truly at the nanoscale with such a limiting factor for the electric-field distribution can solve the non-uniformity issue of future ReRAM.

Abstract The recent progress in the metal‐insulator‐metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO 2 ‐Al 2 O 3 ‐ZrO 2 /TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO 3 , which has a dielectric constant of >100, even at a thickness ∼10 nm. However, there are many technical challenges to overcome before this type of MIM capacitor can be used in mass‐production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the mean time, rutile structure TiO 2 and Al‐doped TiO 2 films might find space to fill the gap between ZAZ and SrTiO 3 MIM capacitors due to their exceptionally high dielectric constant among binary oxides. Achieving a uniform and dense rutile structure is the key technology for the TiO 2 ‐based dielectrics, which depends on having a dense, uniform and smooth RuO 2 layer as bottom electrode. Although the Ru (and RuO 2 ) layers grown by ALD using metal‐organic precursors are promising, recent technological breakthroughs using the RuO 4 precursor made a thin, uniform, and denser Ru and RuO 2 layer on a TiN electrode. A minimum equivalent oxide thickness as small as 0.45 nm with a low enough leakage current was confirmed, even in laboratory scale experiments. The bulk dielectric constant of ALD SrTiO 3 films, grown at 370 °C, was ∼150 even with thicknesses ≤15 nm. The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD SrTiO 3 film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high capacitor density and three‐dimensional structures are necessary.

Al-doped TiO2 thin films to be used in future DRAM capacitors with excellent leakage properties as well as high dielectric constants are fabricated. The next generation stack structured DRAM cell composed of a transistor and a capacitor is shown (see Figure). A large cell capacitance is required for successful operation of DRAMs irrespective of the feature size of the cell. Therefore, as scaling down of the DRAMs proceeds, a higher-k material such as Al-doped TiO2 has to be eventually implemented in the capacitor. Supporting information for this article is available on the WWW under http://www.wiley-vch.de/contents/jc_2089/2008/adma200701085_s.pdf or from the author. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Oxygen-scavenging MoN x converts ALD MoO x into metastable monoclinic MoO 2 , enabling high-k rutile TiO 2 -based capacitors with low leakage and ultralow EOT.

As dynamic random-access memory (DRAM) technology continues to scale down to sub-10 nm nodes, achieving high memory density and enhanced operational performance poses increasing challenges. In particular, maintaining sufficient cell capacitance and minimizing the leakage current density have emerged as key issues. To address these issues, the development of novel electrode materials and carefully engineered interfaces between high-k dielectrics and electrodes is crucial. In this study, thermal atomic layer deposition (ALD) of Sn-incorporated MoO_<i>x</i> (TMO) films was performed using (N^tBu)₂(NMe)₂Mo and Sn(dmamp)₂ as the Mo and Sn precursors, respectively. The growth characteristics of the TMO films, particularly the interaction between the MoO_<i>x</i> and SnO_<i>x</i> subcycles, were systematically investigated. Controlled Sn incorporation into MoO_<i>x</i> successively stabilized the formation of the monoclinic MoO₂ phase, resulting in a smooth surface morphology and enhanced thermal and chemical stability. ALD TMO films were employed as an interface control layer (ICL) in a metal-insulator-metal capacitor to improve the interfacial properties between the (Al-doped) TiO₂ and TiN bottom electrodes. ALD TMO films promoted the in situ crystallization of rutile TiO₂ (with a dielectric constant of up to 156) and effectively suppressed the unwanted formation of a low-k TiO_<i>x</i>N_<i>y</i> layer, resulting in significant equivalent oxide thickness (EOT) scaling. Furthermore, the insertion of the TMO ICL significantly reduced the leakage current density of the (Al-doped) TiO₂ films, which was attributed to the higher work function of TMO (4.7-4.8 eV) compared to that of TiN (4.5 eV) and the minimal formation of defective TiO_<i>x</i>N_<i>y</i>. To evaluate the scalability of the ALD TMO ICL, its thickness was varied from 20 to 1 nm. Remarkably, even at the ultrathin thickness of 1-2 nm, TMO ICL maintained high capacitance and low leakage current density, achieving an EOT of 0.58 nm and leakage current density of 2.4 × 10^-7 A/cm². These results highlight the potential of ALD-grown TMO films as ICLs in next-generation DRAM capacitors.

In high-density crossbar array memory architectures, selector devices play a crucial role in suppressing sneak-path currents and ensuring stable operation. In this study, we propose a pure SiO₂-based selector fabricated using conventional semiconductor processes and materials and experimentally demonstrate its threshold switching (TS) characteristics. Stable TS behavior is verified with an endurance exceeding 10⁹ cycles under repeatable measurement sequences and pulse-driven operations. Interface structure analysis combined with controlled pulse-based electrical characterization reveals that the formation of oxygen vacancies (V_Os), the resulting structural asymmetry, and the dynamic charging behavior of V_Os within the oxide are the key mechanisms governing the TS manifestation. Based on these insights, the optimized pulse conditions are established for reliable TS operation. The proposed selector, featuring a simple undoped oxide structure, can be fabricated at temperatures below 300 °C and offers tunable threshold voltage, enabling excellent integration compatibility with advanced memory devices. This study introduces a selector structure that distinguishes itself from conventional chalcogenide- or metal-oxide-based selectors by combining superior process and device compatibility with structural simplicity, offering a promising pathway toward a highly integrated and CMOS-compatible selector.