발행물
컨퍼런스
16th International Symposium on Quality Electronic Design (ISQED 2015)
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Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC
ISOCC 2014 : 11th International SoC Design Conference
Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models
Great Lakes Symposium on VLSI
A New Methodology for Reduced Cost of Resilience
(L2) IEEE/ACM International Conference on Computer-Aided Design
(L2) High-performance gate sizing with a signoff timer
(L3) 2013 IEEE 31st International Conference on Computer Design
(L3) Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits