주요 논문
3
*2026년 기준 최근 6년 이내 논문에 한해 Impact Factor가 표기됩니다.
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인용수 5
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2024An Inductance-Variation-Insensitive Buck Converter Using a Dynamic Ramp Compensation With Slope Sensing Technique
Dong-Hyun Shin, Chung-Hee Jang, Young-Kyu Kim, Tony Tae-Hyoung Kim, Sukho Lee, Kwang‐Hyun Baek
IF 4.9 (2024)
IEEE Transactions on Circuits & Systems II Express Briefs
This brief introduces a current-mode DC-DC buck converter that operates without performance degradations, even when the inductance value changes. The proposed circuit can be widely utilized to ensure the stable operation of various systems, as inductor values in PMICs may fluctuate despite being identical components. The proposed Inductance-Variation-Insensitive (IVI) buck converter directly senses the rate of change of inductor current and transmits information about the output voltage and inductance to a dynamic ramp generator. The dynamic ramp generator produces a ramp signal proportionate to the sensed inductor current slope, thereby maintaining a deadbeat state and preventing subharmonic oscillations. This innovative approach enables the converter to function seamlessly across a wide range of output values while maintaining overall stability. The proposed buck converter is fabricated using a 0.18 m 1P6M CMOS process, occupying an active area of 0.82 mm2. Experimental results demonstrate its stable operation over a broad range of output voltages, even in the presence of inductance variations, when compared to conventional fixed-ramp approaches. It exhibits a transient response recovery time of 3.9 s for a load change from 50 mA to 350 mA and 4.7 s for the reverse change, from 350 mA to 50 mA. Furthermore, this work achieves a maximum power efficiency of 90.5%, accompanied by an output ripple of less than 30 mV.
https://doi.org/10.1109/tcsii.2024.3374283
Buck converter
Inductor
Inductance
Ripple
Control theory (sociology)
Voltage
Buck–boost converter
Transient (computer programming)
Compensation (psychology)
Generator (circuit theory)
2
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인용수 3
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2024A Reconfigurable Step-Down Switched-Capacitor Power Converter Using Optimized Partial Series-Parallel (OPSP) Topology
Chung-Hee Jang, Dong-Hyun Shin, Young-Kyu Kim, Tony Tae-Hyoung Kim, Sukho Lee, Kwang‐Hyun Baek
IF 4.9 (2024)
IEEE Transactions on Circuits & Systems II Express Briefs
This brief presents a reconfigurable step-down switched-capacitor power converter fabricated using a 180 nm CMOS process for low-power applications. The proposed Optimized Partial Series-Parallel (OPSP) topology aims to achieve an intermediate voltage conversion ratio while more effectively minimizing parasitic capacitor losses. This improvement is realized by eliminating one of the flying capacitors, specially the one responsible for the largest parasitic capacitor voltage swing, distinguishing it from the previously reported Partial Series-Parallel (PSP) topology. Furthermore, the use of NMOS capacitor in conjunction with flying parasitic junction capacitors is also proposed to enhance the capacitor density. This switched-capacitor power converter is capable of delivering a 1.8 V output within an input voltage range spanning from 3.1 V to 4.1 V. Employing the methods outlined in this paper enables the attainment of a peak power conversion efficiency of 83.1% when the load current is 1.8 mA.
https://doi.org/10.1109/tcsii.2024.3354283
Capacitor
Switched capacitor
NMOS logic
Topology (electrical circuits)
Voltage
Electrical engineering
Electronic engineering
Series and parallel circuits
Computer science
Power (physics)
3
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인용수 3
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2023A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process
Dong-Hyun Yoon, Kwang‐Hyun Baek, Tony Tae-Hyoung Kim
IF 4.6 (2023)
IEEE Journal of Solid-State Circuits
Direct-digital frequency synthesizers (DDSs) are highly attractive in wireless communications because of their fast frequency hopping characteristics. Generally, DDSs adopt truncation and thermometer decoding for high-frequency resolution and monotonicity, respectively. However, the truncation causes poor spectral purity due to periodical errors in phase accumulation. Also, the thermometer decoding scheme of digital-to-analog converter (DAC) requires many current sources, which creates large parasitic components and nonlinearity. This article presents several techniques for addressing the above challenges. First, a fixed-weight decoder (FWD) with an auxiliary DAC is proposed to remove the truncation spur in the phase accumulation. Since FWD controls the amplitude regardless of the phase, it removes the periodic errors without significant power increment. Second, the proposed tristate decoding scheme reduces the number of current sources to reduce timing mismatches and capacitances. Finally, a fine current source reusing technique is developed to reduce the number of current sources and power consumption. The proposed DDS was fabricated in a 65-nm CMOS technology. The worst spurious-free dynamic range (SFDR) is 57.35 dBc at 2.5 GHz with a power consumption of 104 mW. The measured figure of merit is 18 124 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX"></tex-math> </inline-formula> 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX"></tex-math> </inline-formula> /W.
https://doi.org/10.1109/jssc.2023.3341040
Spurious-free dynamic range
Integral nonlinearity
CMOS
Truncation (statistics)
Differential nonlinearity
Electronic engineering
Decoding methods
dBc
Computer science
Algorithm