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전체 논문

120

71

An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders
Institute of Electrical and Electronics Engineers, 2011

72

A high-throughput LDPC decoder architecture for high-rate WPAN systems
Institute of Electrical and Electronics Engineers, 2011

73

A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications
Institute of Electrical and Electronics Engineers, 2011

74

Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2011

75

Area-efficient truncated Berlekamp-Massey architecture for Reed-Solomon decoder
IEE-INST ELEC ENG, 2011

76

A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications
2010

77

100GB/S two-iteration concatenated BCH decoder architecture for optical communications
2010

78

High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture
IEEK PUBLICATION CENTER, RM #907 SCIENCE & TECHNOLOGY NEW BLDG, 635-4 YUCKSAM-DONG, SEOUL, SOUTH KOREA, KANGNAM-KU, 135-703, 2010

79

High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2010

80

High throughput four-parallel RS decoder architecture for 60GHz mmWAVE WPAN systems
2010