Next‐generation artificial tactile systems demand seamless integration with neuromorphic architectures to support on‐edge computation and high‐fidelity sensory signal processing. Despite significant advancements, current research remains predominantly focused on optimizing individual sensor elements, and systems utilizing single neuromorphic components encounter inherent limitations in enhancing overall functionality. Here, we present a vertically integrated in‐sensor processing platform, which combines a three‐dimensional antiferroelectric field‐effect transistor (AFEFET) device with an aluminum nitride (AlN) piezoelectric sensor. This innovative architecture leverages a Zr‐rich, leaky antiferroelectric HZO film—a novel material for physical reservoir computing (PRC) devices capable of responding to external stimuli within the microsecond‐to‐millisecond range. We further demonstrate the 3D AFEFET's adaptability by tuning its discharge current via structural modifications, enabling sophisticated multilayered processing. As an integrated in‐sensor processing unit, the 3D AFEFET and AlN sensor array surpass a comparable 2D configuration in both pattern recognition and information density. Our findings showcase a pioneering prototype for future artificial tactile systems, demonstrating the transformative potential of 3D AFEFET PRC devices for advanced neuromorphic applications.

Physically unclonable function (PUF) is a lightweight encryption technique that generates random digital keys (responses) using intrinsic process variations of devices, which is a promising solution for Internet of Things (IoT) security due to its compatibility with constrained resources. Recent attempts to adopt nonvolatile memory (NVM) into PUFs have enhanced stability through a write-back technique that maintains consistent responses from the enrollment phase even under wide environmental variations by storing the response in the NVM device. However, the stability of the previous NVM PUFs is limited by the low on/off ratio of the NVMs. In addition, the circuit required to implement the write-back technique poses challenges of increased area and energy consumption. Considering the hardware limitations and power constraints of IoT devices, this paper proposes a ferroelectric field-effect transistor (FeFET) PUF as a suitable security solution. The high on/off ratio of FeFET and the proposed auto write-back technique that does not require additional circuitry realize the stability improvement (a bit error rate of <0.0001%) under wide environmental variations without incurring area and energy overheads. The negligible off current of FeFET prevents static power consumption, which leads to the lowest energy consumption of 6.70e-15 J during the response generation of the FeFET PUF. In addition, the compact PUF cell composed of two FeFETs achieves a high density of 87.37 F2.

Next‐generation artificial tactile systems demand seamless integration with neuromorphic architectures to support on‐edge computation and high‐fidelity sensory signal processing. Despite significant advancements, current research remains predominantly focused on optimizing individual sensor elements, and systems utilizing single neuromorphic components encounter inherent limitations in enhancing overall functionality. Here, we present a vertically integrated in‐sensor processing platform, which combines a three‐dimensional antiferroelectric field‐effect transistor (AFEFET) device with an aluminum nitride (AlN) piezoelectric sensor. This innovative architecture leverages a Zr‐rich, leaky antiferroelectric HZO film—a novel material for physical reservoir computing (PRC) devices capable of responding to external stimuli within the microsecond‐to‐millisecond range. We further demonstrate the 3D AFEFET's adaptability by tuning its discharge current via structural modifications, enabling sophisticated multilayered processing. As an integrated in‐sensor processing unit, the 3D AFEFET and AlN sensor array surpass a comparable 2D configuration in both pattern recognition and information density. Our findings showcase a pioneering prototype for future artificial tactile systems, demonstrating the transformative potential of 3D AFEFET PRC devices for advanced neuromorphic applications.

Physically unclonable function (PUF) is a lightweight encryption technique that generates random digital keys (responses) using intrinsic process variations of devices, which is a promising solution for Internet of Things (IoT) security due to its compatibility with constrained resources. Recent attempts to adopt nonvolatile memory (NVM) into PUFs have enhanced stability through a write-back technique that maintains consistent responses from the enrollment phase even under wide environmental variations by storing the response in the NVM device. However, the stability of the previous NVM PUFs is limited by the low on/off ratio of the NVMs. In addition, the circuit required to implement the write-back technique poses challenges of increased area and energy consumption. Considering the hardware limitations and power constraints of IoT devices, this paper proposes a ferroelectric field-effect transistor (FeFET) PUF as a suitable security solution. The high on/off ratio of FeFET and the proposed auto write-back technique that does not require additional circuitry realize the stability improvement (a bit error rate of <0.0001%) under wide environmental variations without incurring area and energy overheads. The negligible off current of FeFET prevents static power consumption, which leads to the lowest energy consumption of 6.70e-15 J during the response generation of the FeFET PUF. In addition, the compact PUF cell composed of two FeFETs achieves a high density of 87.37 F2.

Abstract Flash memory is a promising candidate for use in in‐memory computing (IMC) owing to its multistate operations, high on/off ratio, non‐volatility, and the maturity of device technologies. However, its high operation voltage, slow operation speed, and string array structure severely degrade the energy efficiency of IMC. To address these challenges, a novel negative capacitance‐flash (NC‐flash) memory‐based IMC architecture is proposed. To stabilize and utilize the negative capacitance (NC) effect, a HfO 2 ‐based reversible single‐domain ferroelectric (RSFE) layer is developed by coupling the flexoelectric and surface effects, which generates a large internal field and surface polarization pinning. Furthermore, NC‐flash memory is demonstrated for the first time by introducing a RSFE and dielectric heterostructure layer in which the NC effect is stabilized as a blocking layer. Consequently, an energy‐efficient and high‐throughput IMC is successfully demonstrated using an AND flash‐like cell arrangement and source‐follower/charge‐sharing vector‐matrix multiplication operation on a high‐performance NC‐flash memory.

This article presents an NMOS header assist cell (NHAC) that lowers static random access memory (SRAM) minimum operating voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>MIN</roman></sub>) with minimal power overhead for low-power applications, even in the case of increased interconnect resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub>) with technology scaling. The proposed NHAC, featuring a Bitcell-compatible layout, is inserted between cell arrays to supply power by dividing cell-power (CVDD) into sub-arrays without additional dummy cells or white space. NHAC improves write ability even in high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub> cases, thanks to the continuous self-collapse of the CVDD voltage by supplying cell power through NMOS during write operations. The NMOS header in NHAC prevents excessive CVDD voltage collapse, thus ensuring the dynamic data retention stability of column half-selected cells (CHSCs). Additionally, by enabling all NHACs in sleep mode, the CVDD voltage can be clamped below the supply voltage, thereby reducing bitcell retention leakage without additional area costs. SRAM macros with additional resistors were fabricated using a 14 nm FinFET process to measure the impact of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub> on the write assist circuits. NHAC achieves a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>MIN</roman></sub> improvement of 210 mV with 4% power overhead, even in the high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub> case. In sleep mode, NHAC reduces bitcell retention leakage by 25% at 0.65 V and up to 61% at 1 V. NHAC demonstrates improved write <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>MIN</roman></sub> similar to transient voltage collapse (TVC) write assist. Additionally, it achieves low-power overhead similar to self-induced voltage collapse (SIC) write assist.

This article presents DPe-CIM, a 4T-1C dual-port embedded dynamic random access memory (eDRAM)-based compute-in-memory (CIM) macro with adaptive refresh and data conversion reduction. DPe-CIM proposes four key features that improve area and energy efficiency: 1) dual-port eDRAM cell (DPC) separates the multiply-and-accumulate (MAC) and refresh ports, enabling simultaneous MAC and refresh (SMR) operation to eliminate wasted cycles for refresh; 2) adaptive refresh tracking (ART) eliminates unnecessary refresh power consumption; 3) bitline (BL) embedded DAC (BLe-DAC) enhances area and energy efficiency with BL capacitance reuse; 4) output-boosting ADC (OB-ADC) with charge analog adder (CAA) reduces ADC precision and number of ADC per row without accuracy loss to save area and energy in ADC, thereby overcoming CIM efficiency wall. The DPe-CIM is fabricated in 28-nm CMOS technology and occupies 0.0496 mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^2$</tex-math> </inline-formula> with 72-kb cell capacity. Its measured memory density is 1.42 Mb/mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^2$</tex-math> </inline-formula>, reaches a peak MAC density of 13.85 TOPS/mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^2$</tex-math> </inline-formula>, and a peak energy efficiency of 505.83 TOPS/W performing 4-b−4-b operations. DPe-CIM achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.56\times$</tex-math> </inline-formula> higher computing efficiency figure of merit (FoM) than the previous CIM architectures.

We propose two innovative sense amplifiers, the asymmetric voltage latched-type sense amplifier (A-VLSA) and the ultra-low swing bitline sense amplifier (ULS-SA), to enhance read performance and reduce power consumption in the non-hierarchical BL 2-port 8-transistor SRAM (2P-SRAM). A-VLSA minimizes offset voltage through a MOS capacitor-based asymmetric operation, while ULS-SA achieves reduced read power by adopting clipped precharging and a charge-sharing read mechanism without incurring delay penalties. Measurement results demonstrate that A-VLSA (ULS-SA) achieves 63% (37%) and 61% (63%) lower energy-delay product (EDP) at V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DD</b></sub> = 0.8V and 0.6V, respectively, with a 24% (43%) smaller area compared to the previous pseudo-differential asymmetric current latched-type sense amplifier (A-CLSA). These improvements address key limitations of prior approaches, delivering significant advancements in both power efficiency and read performance, especially under high cell density conditions.

With the increase in memory density and scaling down of the DRAM process, the length of the global IO pairs (GIO and GIOB) and the offset voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{OS}}$</tex-math> </inline-formula>) have increased. This degrades the power consumption and sensing time (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\text{SEN}}$</tex-math> </inline-formula>) of IO sense amplifiers (IOSAs) that sense the differential input voltage via long GIO pairs (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\text{GIO}}$</tex-math> </inline-formula>). Conventional IOSAs use the self-time logic, hybrid IOSA, and GIO switches to reduce the power consumption of IOSA. However, they do not consider <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{OS}}$</tex-math> </inline-formula> of the IOSA, which requires a larger <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\text{GIO}}$</tex-math> </inline-formula> for robust IOSA sensing operations, increasing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\text{SEN}}$</tex-math> </inline-formula> to develop a large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\text{GIO}}$</tex-math> </inline-formula> and increasing the power consumption to pre-charge these discharged GIO pairs. To mitigate these issues, offset cancellation (OC)-IOSA has been proposed. However, since two large coupling-capacitor-based OC-IOSAs transfer <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\text{GIO}}$</tex-math> </inline-formula> via capacitive coupling, it suffers from input voltage attenuation, severe area overhead, and static current. This work proposes a single capacitor-based direct input transfer static current-free pre-sensing IOSA (SCFP-IOSA) to reduce <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{OS}}$</tex-math> </inline-formula> and power consumption with a small area and high speed. The direct input transfer scheme is adopted in SCFP-IOSA, which removes input voltage attenuation and does not require large capacitors, thereby enhancing the sensing margin and relieving area overhead. In addition, a novel static current-free pre-sensing, which uses RC delay exponential nature, is proposed that not only pre-amplifies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\text{GIO}}$</tex-math> </inline-formula> to enhance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{OS}}$</tex-math> </inline-formula> tolerance but also reduces power consumption by removing static current during the pre-sense (PS) operation. The simultaneous coupling down and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{\text{GIO}}$</tex-math> </inline-formula> developing operation also contribute to the fast sensing operation of SCFP-IOSA. According to the measurement on the experimental chip fabricated in a 28-nm CMOS technology, SCFP-IOSA achieves three times lower <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\text{OS}}$</tex-math> </inline-formula> of 4.42 mV, 2.9 times lower power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.15\mu$</tex-math> </inline-formula>W, and 1.3 times faster <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\text{SEN}}$</tex-math> </inline-formula> of 3.75 ns with 4.46 times smaller area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.28\mu$</tex-math> </inline-formula>m<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compared with the state-of-the-art OC-IOSA.

This paper proposes an explainable multi-modal deep learning framework for early prediction of signal integrity (SI), specifically eye height (EH) and eye width (EW). The model fuses heterogeneous measurement data across hierarchical stages (module, package, and system) to anticipate final eye margin outcomes before full system integration. The application of Shapley additive explanations and integrated gradients converts the model into an explainable form, which clarifies the leading contributors to EH and EW margins. The framework, evaluated on 1a-nm 16Gb DDR5 DRAM, achieves approximately 89% accuracy in predicting EH and 66.5% for EW. These results demonstrate an effective screening tool to detect potential SI margin issues in early stages, reducing the burden of exhaustive system-level validation.

The general approach to suppress leakage in static random access memory (SRAM) is to use a low voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{L}}$</tex-math> </inline-formula>), generated by a low-dropout regulator (LDO), as the cell supply voltage (CVDD) of SRAM array in the standby mode. However, the effectiveness of lowering CVDD is constrained by the area and power overhead introduced by the LDO, as well as the additional latency and power consumption incurred during mode switching. This work presents a fully voltage-stacked (FVS) SRAM that reduces leakage power with internally generated intermediate voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{MID}}$</tex-math> </inline-formula>) by stacking SRAM arrays. The FVS SRAM consists of a foundry high-density (HD) cell and a pMOS pass-gate (PG) cell having the same metal pattern and size as the HD cell, ensuring compatibility across various process nodes. In addition, the FVS SRAM reduces minimum operating voltage and access energy by the intermediate cell voltage (ICV) assist technique and charge-sharing-based precharge, respectively. The silicon measurement results from a 14-nm FinFET test chip demonstrate that the FVS SRAM achieves a leakage power of 5.34 pW/bit and an access energy of 24.6 fJ/bit at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{MIN}}=0.5$</tex-math> </inline-formula>V. Compared to conventional non-stacked SRAM, the FVS SRAM exhibits 29%–59% and 10%–21% reduction in leakage power and access energy across VDD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=0.6$</tex-math> </inline-formula>–0.8 V.