발행물
컨퍼런스
International Conference on Solid State Devices and Materials
,
Design and Implementation of Read-Compare-Write circuits for low power Multi-Gigabit DRAM
2001 VLSI Circuits Symposium
Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications
480ps 64-bit Race Logic adder
A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth
A 120mW embedded 3D graphics rendering engine with 6Mb logically local frame-buffer and 3.2GByte/s run-time reconfigurable bus for PDA-chip