발행물
컨퍼런스
IEEE International Symposium on Circuits and Systems
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A Comparative Analysis of a DDR-SDRAM and a D-RDRAM usind a POPeye Simulator
Asia and South Pacific Design Automation Conference 2001
Single chip 3D rendering engine integrating embedded DRAM frame buffer and hierarchical octet tree (MOT) array processor with bandwidth amplification
Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems
One chip - Low power digital-TCXO with sub-ppm accuracy
670 ps, 64 bit dynamic low-power adder design
A 670ps, 64bit dynamic low-power adder design