발행물
컨퍼런스
ESSCIRC 2000
2000
,
A Single Bit line Writng Scheme for Low Power Reconfigurable I/O DRAM MacroAuthor
ISCAS 2000
One chip - low power Digital-TCXO with Sub-ppm AccuracyAuthor
A 670ps, 64bit Dynamic Low-Power Adder DesignAuthor
ICVC 2000
POPeye: A System Analysis Tool for DRAM Performance MeasurementAuthor
ISSCC 2000
A 330MHz Low Jitter Fast Locking Direct Skew Compensation DLLAuthor