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39

21

READ:Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution
H. Han, J. Chung, J.-S. Yang
IEEE Transactions on Computers, 2017

22

Clock Network Optimization with Multi-bit Flip-flop Generation Considering Multi-corner Multi-mode Timing Constraint
T. Lee, D.Z. Pan, J.-S. Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017

23

Enhancing Test Compression with Dependency Analysis for Multiple Expansion Ratios
T. Lee, N.A. Touba, J.-S. Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016

24

Studying Trapped Tunneling-Electron Migration due to Program and Erase Cycles in NAND Flash
M. Kang, J.-S. Yang, I.K. Chang
IEEE Electron Device Letters, 2016

25

Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC
H. Han, N.A. Touba, J.-S. Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015

26

Enhancing Superset X-Canceling Method with Relaxed Constraints on Fault Observation
J.-S. Yang, J. Chung, N.A. Touba
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015

27

Physical Aware Approaches for Speeding up Scan Shift Operation in SoC
T. H. Lee, I. J. Chang, C. Lee, J.-S. Yang
ETRI Journal, 2015

28

3D Probe : Low-cost Variation Modeling Using Inter-test-item Correlations
J.-Y. Chang, Y. Kim, J.-S. Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014

29

Utilizing ATE Vector Repeat With Linear Decompressor For Test Vector Compression
J.-S. Yang, J. Lee, N.A. Touba
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014

30

Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops
J.-S. Yang, N.A. Touba
ETRI Journal, 2014