발행물

논문
컨퍼런스

전체 논문

39

31

Dynamic Self Repair Architectures for Defective Through Silicon Vias
J.-S. Yang, T.H. Han, D. Kobla, E. L. Ju
ETRI Journal, 2014

32

Low-Power Shared Memory Architecture Power Mode for Mobile System-on-Chip
J. Kim, J.-H. Huh, S.-Y. Kim, S.W. Kim, J.-S. Yang
IEICE Electronics Express, 2014

33

Communication-aware custom topology generation for VFI network-on-chip
C.-L. Li, J.H. Lee, J.-S Yang, T.H. Han
IEICE Electronics Express, 2014

34

Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion
J.-S. Yang, I.K. Chang
IEICE Transactions on Electronics, 2013

35

Bit-error Rate Improvement of TLC NAND Flash using State Re-ordering
I.K. Chang, J.-S. Yang
IEICE Electronics Express, 2013

36

Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug
J.-S. Yang, N.A. Touba
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013

37

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops
J.-S. Yang, N.A. Touba
IEEE Transactions on Computers, 2012

38

X-Canceling MISR Architectures for Output Response Compaction with Unknown Values
J.-S. Yang, N.A. Touba
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012

39

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis
J.-S. Yang, N.A. Touba
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012