This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/$C$-noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array.

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/$C$-noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array.

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm2, including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

This paper presents a fully dynamic discrete-time (DT) delta-sigma modulator (DSM) leveraging a floating inverter amplifier (FIA)-based dynamic loop filter and digital noise coupling (DNC) to enhance the power efficiency of the DT DSM for various sensor applications. Fabricated in a 28-nm CMOS process, the proposed architecture achieves 98.6-dB SNDR in 25-kHz bandwidth (BW), while consuming only$71.7\mu \mathrm{W}$operating at 6.4 MS/s, resulting in Schreier Figure of Merit (${FoM}_{\text{S}}$of 184 dB and Walden FoM (${FoM}_{\text{W }}$) of 20.6 fJ/conv.-step.

This paper proposes a continuous-time (CT) tracking-zoom (TZ) incremental ADC (I - ADC) that reuses a quantizer for both the coarse SAR and fine DSM stages. The TZ I-ADC addresses the input bandwidth (BW) limitation issue with simple DAC code update. A residue-gain (RG) switching technique is proposed to mitigate the inconsistent signal transfer function (STF) in the fine CT incremental DSM (I-DSM). A digital noise-coupling-feedforward (DNC-FF) architecture is proposed to reduce the out-of-band gain (OBG). Fabricated in a 180nm CMOS process, the prototype consumes 2.52mW under a 1.8V supply, achieving 99-dB DR. 93.8-dB SNDR. and 102.5-dB SFDR.

Over the past decade, SAR ADCs have extended their territory to higher resolution with noise-shaping (NS). lncorporated with a pipeline architecture, the conversion speed could also be improved. However, as the accuracy requirements for the residue amplifier (RA) in the pipeline architecture are often very costly, several techniques have been reported to avoid power and gain-calibration burden on the RA: The gain-error shaping (GES) technique [1] shapes the quantization leakage error caused by the RA gain-error, but some additional analog components and digital processing are required. The 2-0 MASH structure [2] has an inherent RA gain-error tolerance, but the possible mismatch between the analog and the digital NTFs would limit the performance as in typical MASH DSMs. Motivated by the issues mentioned above, this paper introduces a $2^{\mathrm{nd}}-$order noiseshaping interpolating-SAR (NS ISAR) ADC for the backend ADC in dual-residue (D-R) pipeline architecture [3], where there is no RA gain accuracy burden. A Segmentation technique for the capacitive interpolating DAC is also proposed to enhance the achievable resolution (+20dB SONR improvement) by solving the parasitic sensitiveness of the capacitive interpolation. With the RA burden alleviated in power, calibration, and linearity, the prototype pipeline ADC in a 180nm CMOS process achieves an SNDR of 81. 2dB in a 1. 5MHz BW at an OSR of 8 without any calibration.

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

We demonstrated an organic and oxide hybrid CMOS inverter with the solution-processed semiconductor and source/drain electrodes. For the solution-processed n - and p -type semiconductor, InGaZnO solution and TIPS-pentacene/P α MS blend were spin-coated respectively while Silver ink and PEDOT:PSS solution were drop-casted with the help of the bank to serve as source/drain electrodes. The InGaZnO and the TIPS-pentacene transistors show typical n - and p -type transistor operations with low off-current. Based on the combination of the solution-processed n - and p -type transistors, full-swing characteristic curve with low static current of the hybrid CMOS were obtained.

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC is presented for the application of local activation imaging in nerve section. It is increasingly known that the monitoring and control of nerve signals can improve physical and mental health. Major nerves, such as the vagus nerve and the sciatic nerve, consist of a bundle of fascicles. Therefore, to accurately control a particular application without any side effects, we need to know exactly which fascicle was activated. The only way to find locally activated fascicle is to use electrical impedance tomography (EIT). The ASIC to be introduced is designed for neural EIT applications. A neural impedance sensing ASIC was implemented using CMOS 180-nm process technology. The integrated input referred noise was calculated to be 0.46 μVrms (noise floor 10.3 nVrms/rt Hz) in the measured noise spectrum. At an input of 80 mV, the squared correlation coefficient for linear regression was 0.99998. The amplification gain uniformity of 32 channels was in the range of + 0.23% and - 0.29%. Using the resistor phantom, the simplest model of nerve, it was verified that a single readout channel could detect a signal-to- noise ratio of 75.6 dB or more. Through the reservoir phantom, real-time EIT images were reconstructed at a rate of 8.3 frames per second. The developed ASIC has been applied to in vivo experiments with rat sciatic nerves, and signal processing is currently underway to obtain activated nerve cross-sectional images. The developed ASIC was also applied to in-vivo experiments with rat sciatic nerves, and signal processing is currently underway to obtain locally activated nerve cross-sectional images.