Diffusion-rounded CMOS for Improving Both Ion and Ioff Characteristics

Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion

Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation

Novel 8-bit IMC Approximate Adders with Advanced Error Mitigation Techniques

Improving Error Metrics in Approximate Multipliers with an Error Recovery Unit

Design of an Approximate Multiplier with Error Recovery and Hardware Optimization

Lightweight Binary Neural Networks for Edge Devices

Design of Stochastic Computing - based Multiplier Circuit using Low Power and High Performance D Flip-Flop

Advanced Quantized BNNs for Edge Devices

Enhancing Accuracy of Approximate Adders with Novel Error Reduction Unit