발행물

전체 논문

143

81

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor
Lee, J (Lee, Jaemin), Ryu, M (Ryu, Myunghwan), Kim, Y (Kim, Youngmin)
IEICE ELECTRONICS EXPRESS, 2015

82

A High Resolution and High Linearity 45 nm CMOS Fully Digital Voltage Se nsor for Low Power Applications
김영민, 류명환
IEICE Electronics Express, 2013

83

Intra-gate Length Biasing for Leakage Optimization in 45nm Technology No de
강예성, 김영민
IEICE Transaction on Fundamentals, 2013

84

Trapezoidal approximation for on-current modeling of 45-nm non-rectiline ar gate shape
김영민, 류명환
IEICE Electronics Express, 2013

85

TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC
HUNG VIET NGUYEN, 류명환, 김영민, 0, 0, 0
IEICE TRANSACTIONS ON ELECTRONICS, 2012

86

A novel methodology for speeding up IC performance in 32nm FinFET
김영민, HUNG VIET NGUYEN, 류명환
IEICE Electronics Express, 2012

87

Diffusion-rounded CMOS for Improving Both Ion and Ioff Characteristics
김영민, 류명환, HUNG VIET NGUYEN
IEICE Electronics Express, 2011

88

Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion
Kim Y (Kim, Youngmin), Petranovic D (Petranovic, Dusa, Sylvester D (Sylvester, Dennis
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009

89

Investigation of diffusion rounding for post-lithography analysis
Gupta, P., Kahng, A.B., Kim, Y., Shah, S., Sylvester, D.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, art. no., 2008

90

Shaping gate channels for improved devices
Gupta, P., Kahng, A.B., Kim, Y., Shah, S., Sylvester, D.
Proceedings of SPIE - The International Society for Optical Engineering, 2008