This paper proposes a 48V to 1-1.2V two-stage converter, consisting of a high-voltage (HV) switched-capacitor (SC) stage and a low-voltage (LV) buck converter stage. By fixing the duty-cycle (D) of the HV SC at 0.5, peak current in HV SC is optimized, minimizing conduction loss (PCON) in the HV SC. In addition, the continuous capacitor-current (IC) path in the LV stage enables removing a middle-capacitor and improves transient response. The proposed converter supports up to a 4A maximum load current and achieves peak efficiencies of 90.9% at output voltage (VO) of 1V and 92.1% at VO of 1.2V.

This letter proposes an n-type output capacitorless low-dropout regulator (LDO) with high power supply rejection (PSR) and fast transient response. To enhance both the performances, a multiple-feedback loop structure is proposed. The LDO obtained a PSR of –40 dB (–25 dB) at 1 MHz with load currents of 100 mA (600 mA). The LDO achieved an undershoot of 116 mV when the load changes from 1 to 600 mA, while consuming a quiescent current of 27.5 μA. The chip was fabricated in the 180-nm CMOS process with an area of 0.063 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

This paper proposes a 48V to 1-1.2V two-stage converter, consisting of a high-voltage (HV) switched-capacitor (SC) stage and a low-voltage (LV) buck converter stage. By fixing the duty-cycle (D) of the HV SC at 0.5, peak current in HV SC is optimized, minimizing conduction loss (PCON) in the HV SC. In addition, the continuous capacitor-current (IC) path in the LV stage enables removing a middle-capacitor and improves transient response. The proposed converter supports up to a 4A maximum load current and achieves peak efficiencies of 90.9% at output voltage (VO) of 1V and 92.1% at VO of 1.2V.

This letter proposes an n-type output capacitorless low-dropout regulator (LDO) with high power supply rejection (PSR) and fast transient response. To enhance both the performances, a multiple-feedback loop structure is proposed. The LDO obtained a PSR of –40 dB (–25 dB) at 1 MHz with load currents of 100 mA (600 mA). The LDO achieved an undershoot of 116 mV when the load changes from 1 to 600 mA, while consuming a quiescent current of 27.5 μA. The chip was fabricated in the 180-nm CMOS process with an area of 0.063 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

This letter introduces a maximum power point tracking (MPPT) technique for photovoltaic (PV) energy harvesting (EH) systems to enhance the end-to-end efficiency ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E-E</sub> ) when the output power of PV cell ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PV,MAX</sub> ) is low. A ripple-based PV cell current sensing and a time-domain multiplication are proposed to monitor the PV cell power delivered to the charger, which reduces the controller power consumption ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CTR</sub> ). The PV EH system with the proposed MPPT method is implemented in a 180-nm CMOS process. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CTR</sub> is 1.34 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> W. The measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E-E</sub> at low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PV,MAX</sub> (13 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> W) is 88%. The measured peak <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E-E</sub> is 94.4% at 82 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> W.

This paper provides a comprehensive review of power management circuit techniques for millimeter-scale biomedical sensing systems, which operate under strict power and energy constraints. It begins by introducing a miniature sensing platform and outlining the key challenges associated with limited energy availability in such ultra-small devices. The discussion then highlights advances in circuit design for efficient power conversion, battery management, ambient energy harvesting, and wireless power transfer. By examining these techniques, the paper aims to clarify the major design challenges and emerging solutions that are driving the development of next-generation miniature biomedical electronics.

This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>m CMOS process.

This brief proposed an imbalanced inductor-current buck (IIB) converter. The proposed IIB converter has two inductor current paths. The IIB converter provides majority of the load current through a current path composed of low voltage transistors and minority of the load current through the current path composed of high voltage transistors, which becomes further as voltage conversion ratio decreases. Therefore, the IIB converter reduces conduction loss as the voltage conversion ratio decreases, which is considerably important in low voltage applications. In addition, since this converter uses a flying capacitor network behind the inductor, it is invulnerable to the input voltage variation. The proposed converter has peak efficiencies of 90.7% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{IN}}=12$ </tex-math></inline-formula> V, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{O}}=0.6$ </tex-math></inline-formula> V, and 85.6% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{IN}}=12$ </tex-math></inline-formula> V, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{O}}=0.3$ </tex-math></inline-formula> V. The chip was fabricated in 130-nm BCD process with an area of 6.177 mm2.

This article presents a fully integrated step-down switched-capacitor (SC) converter with nine voltage conversion ratios (VCRs) that regulates an output load voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{OUT}}$ </tex-math></inline-formula>) of 0.1–3.67 V with an input voltage of 2.5–5 V. The proposed converter employs 5-V metal-insulator–metal capacitors and 1.8-V native MOSFET capacitors to achieve both power density and conversion efficiency that are suitable for the Internet-of-Things (IoT) applications. In addition, the power stage is operated by the proposed overlapped-conversion-ratio modulation (OCRM), which prevents the severe closed-loop efficiency loss caused by conventional VCR control schemes. Thus, the proposed converter regulates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{OUT}}$ </tex-math></inline-formula> through digitally controlled 15 nine-ratio SC cells, enabling the frequency-scalable power conversion operation. With a 180-nm CMOS process, the proposed converter achieves 87% peak efficiency and the maximum output power of 421 mW.

This paper proposes a dual loop low-dropout regulator (LDO) for heavy load current (I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{L}}$ </tex-math></inline-formula>). The proposed LDO features a fast load transient response and wide output capacitor (C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula>) range. The proposed dynamic negative feedback loop (DNFL) enhances the transient response by reducing the undershoot and widening the bandwidth. The transient response is improved further by the proposed dynamic G<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{m}}$ </tex-math></inline-formula> boosting error amplifier. The C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula> range gets wider thanks to the proposed DNFL, which introduces an additional zero in the feedback loop. The zero secures stability in a wide C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula> range. The prototype of the proposed LDO is fabricated in a 0.5-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> m CMOS process. The input voltage (V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{IN}}$ </tex-math></inline-formula>) ranges from 2.7 to 4.2 V, while the output voltage (V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula>) ranges from 2.4 to 4.0 V. The maximum I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{L}}$ </tex-math></inline-formula> is 2 A. The prototype provides enough phase margin across a C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula> range from 0 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\mu$ </tex-math></inline-formula> F. The measured results show a 68-mV undershoot with a load current of 2.5 A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\mu$ </tex-math></inline-formula> s on a 0-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> F C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula> capacitor. When the C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula> is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\mu$ </tex-math></inline-formula> F under the same conditions, the proposed LDO features an undershoot of 13 mV. The proposed LDO achieves the best FoM among the state-of-the-art LDOs without and with the off-chip C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula>. In cases where the off-chip C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula> is not employed, the achieved FoM is 5.228 ps<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot V/\mu$ </tex-math></inline-formula> m2. When using the off-chip C<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf{O}}$ </tex-math></inline-formula>, the FoM is 0.624 ps/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> m2.

This article presents a single-inductor bipolar-output (SIBO) converter for active-matrix organic light-emitting diode (AMOLED) displays to reduce output ripples and enhance power conversion efficiency (PCE). We propose the simultaneous energy transferring SIBO (SETSIBO) converter, which generates bipolar outputs with only a two-phase operation and does not require additional switching. The hybrid power stage with a flying capacitor and two-phase operation reduces the dc value of the inductor current, which mitigates conduction losses and output ripples; moreover, the hybrid power stage allows the high-voltage switches in the conventional converters to be replaced by low-voltage switches. The inductor current reduction and the low-voltage power switch use improve the PCE. This article analyzes the proposed converter’s output ripple reduction and the PCE improvements; furthermore, the load imbalance is effectively compensated with the proposed SETSIBO converter. The prototype of the proposed SETSIBO is fabricated in a 0.5-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The measured ripples at positive and negative outputs are 24.5 and 28 mV, respectively, with a 300 mA load current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{o}}$ </tex-math></inline-formula>. The measured peak PCE is 94.1%, and the active area is 1.46 mm2.