This paper presents a lightweight and secure data communication protocol tailored for resource-constrained IoT environments. The proposed method integrates Challenge-Response Pair (CRP) Physically Unclonable Functions (PUFs) and a True Random Number Generator (TRNG) to eliminate the need for non-volatile key storage, thereby significantly enhancing resistance against physical attacks and key extraction threats. In contrast to conventional public key authentication methods such as those employed in Pretty Good Privacy (PGP), the protocol replaces asymmetric key operations with CRP-PUFs and hash-based message authentication codes (HMACs), effectively removing the need for key pair generation, key distribution, and private key encryption. To ensure stability in PUF responses under environmental variations, the protocol applies majority voting and BCH error correction codes. It further leverages a large CRP space and incorporates dynamic CRP updates to ensure backward secrecy. In addition, elliptic curve cryptography (ECC) point validation is used to defend against fault injection attacks, collectively offering strong resistance against cloning, brute-force, and implementation-level attacks. While preserving the core cryptographic functions of PGP—such as session key wrapping, ECDSA-based digital signatures, and AES encryption—the proposed protocol dynamically derives all secret keys from hardware-based entropy sources. As a result, it achieves comprehensive security guarantees including authentication, integrity, confidentiality, and non-repudiation, while significantly reducing computational complexity and authentication latency compared to conventional ECC-based schemes. The protocol’s correctness and security are formally verified using ProVerif and Mao-Boyd logic, and its practical feasibility is demonstrated through a compact single-chip implementation, making it highly suitable for real-world industrial IoT deployments.

This brief proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the oscillator at the fundamental frequency while increasing the output power at the second harmonic by enabling a larger transistor size and minimizing the common-mode output conductance. Implemented in the 28-nm CMOS technology, the proposed 270-GHz oscillator achieves a peak output power of −3.2 dBm, a peak dc-to-RF efficiency of 0.81% and phase noise values of −56.8, −84.68 and −90.12 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offsets, respectively.

This paper presents a lightweight and secure data communication protocol tailored for resource-constrained IoT environments. The proposed method integrates Challenge-Response Pair (CRP) Physically Unclonable Functions (PUFs) and a True Random Number Generator (TRNG) to eliminate the need for non-volatile key storage, thereby significantly enhancing resistance against physical attacks and key extraction threats. In contrast to conventional public key authentication methods such as those employed in Pretty Good Privacy (PGP), the protocol replaces asymmetric key operations with CRP-PUFs and hash-based message authentication codes (HMACs), effectively removing the need for key pair generation, key distribution, and private key encryption. To ensure stability in PUF responses under environmental variations, the protocol applies majority voting and BCH error correction codes. It further leverages a large CRP space and incorporates dynamic CRP updates to ensure backward secrecy. In addition, elliptic curve cryptography (ECC) point validation is used to defend against fault injection attacks, collectively offering strong resistance against cloning, brute-force, and implementation-level attacks. While preserving the core cryptographic functions of PGP—such as session key wrapping, ECDSA-based digital signatures, and AES encryption—the proposed protocol dynamically derives all secret keys from hardware-based entropy sources. As a result, it achieves comprehensive security guarantees including authentication, integrity, confidentiality, and non-repudiation, while significantly reducing computational complexity and authentication latency compared to conventional ECC-based schemes. The protocol’s correctness and security are formally verified using ProVerif and Mao-Boyd logic, and its practical feasibility is demonstrated through a compact single-chip implementation, making it highly suitable for real-world industrial IoT deployments.

This brief proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the oscillator at the fundamental frequency while increasing the output power at the second harmonic by enabling a larger transistor size and minimizing the common-mode output conductance. Implemented in the 28-nm CMOS technology, the proposed 270-GHz oscillator achieves a peak output power of −3.2 dBm, a peak dc-to-RF efficiency of 0.81% and phase noise values of −56.8, −84.68 and −90.12 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offsets, respectively.

This brief presents a triple-times-sensitive light detection sensor. The proposed sensor performs faster initialization starting from a power-up sequence, caused by the additional delay-cell logic. Furthermore, the finger- and well-type photodiodes detect light more quickly than a conventional structure while occupying the same active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50\times 50\mu m{}^2$ </tex-math></inline-formula>. The finger-type structure photodiode demonstrates an external quantum efficiency (EQE) of 76%, responsivity (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R$ </tex-math></inline-formula>) of 0.336 A/W, specific detectivity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(D^{\ast })$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.814\times 10^{11}$ </tex-math></inline-formula> Jones, and noise equivalent power (NEP) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.599\times 10^{-17}$ </tex-math></inline-formula> W with under 550 nm illumination at reverse bias of 1.8 V, which are derived from TCAD simulation results. Both prototype light detection sensor with finger- and well-type photodiodes are implemented in a 180 nm standard CMOS technology (1P6M) and achieved about 3 and 1.3 times faster light detection speed than the conventional structure in optical experiment.

The NIST SP 800-22 test suite is the generally accepted standard for Random Number Generator (RNG) evaluation. However, applying default parameters leads to Type I errors (false rejections) due to approximation errors and parameter sensitivity inherent in Level-1 statistic computation. While prior studies have analyzed these error sources, a systematic methodology to optimize parameters at this fundamental stage remains absent. To address this, we propose a parameter optimization method that mitigates structural Type I errors in the Frequency, Cumulative Sums, and Non-overlapping Template Matching tests. Specifically, for the Frequency and Cumulative Sums tests, we derive analytical pass thresholds from the test formulas and align them with the statistically modeled maximum values of the observed statistics to identify a stable pass region <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(n)</i>. In contrast, for the Non-overlapping Template Matching test, we employ a parameter sweep based on sensitivity analysis to determine the optimal parameter set <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(n,N)</i>. This approach minimizes approximation errors and resolves the hypersensitivity to strict decision boundaries, while securing sufficient statistical margins. Verification using a 28 nm CSRO-based TRNG confirms that optimized parameters achieve a 100 % pass rate across all chips, significantly improving upon the 72 % minimum pass rate observed with default parameters. These results indicate that the proposed optimization effectively mitigates structural Type I errors without compromising test sensitivity, enabling the evaluation to strictly target actual deficiencies. Furthermore, the proposed method is generally applicable to varying hardware implementations, allowing researchers to derive optimal verification parameters tailored to their specific entropy characteristics.

This brief presents a high-speed quantum random number generator (QRNG) based on the Quantum Random FlipFlop (QRFF) architecture, utilizing two single-photon avalanche diodes (SPADs) per pixel. The design is implemented using the Samsung 28 nm CMOS process. Each pixel integrates a pair of SPAD detectors, following the QRFF model, enabling a significant improvement in output speed compared to conventional QRFF configurations using a single detector. Experimental results demonstrate that a single pixel achieves a throughput of up to 2 Mbps. Furthermore, the generated random numbers successfully pass the NIST statistical test suite without requiring any postprocessing.

This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes. The measurements show that only a small number of measured TRNG samples passed the randomness NIST SP 800-22 tests, which is a common problem, not only with the proposed TRNG but also with other TRNG structures. To solve this issue, a lightweight post-processing algorithm using the Photon hash function was newly applied to the proposed TRNGs topology. The lightweight Photon hash function-based post-processing was implemented with the proposed TRNG topology in a 28 nm CMOS process. The design occupies 16,498 µm², with a throughput of 0.0142 Mbps and power consumption of 31.12 mW. Measurements showed significant improvement, with a 50% increase in chips passing the NIST SP 800-22 tests. Compared with the conventional DRBG post-processing method, the proposed lightweight Photon post-processing reduces area occupation by five times and power consumption by 65%.

This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of 1.2 × 104 F2/bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs.

This work reports a concurrent dual-band amplifier with an extensive spacing between the two bands by adopting a proposed dual-frequency maximum achievable gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$G_{\max }$</tex-math></inline-formula> ) core with dual-band matching. The proposed dual-frequency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$G_{\max }$</tex-math></inline-formula> -core can expand the difference between the two target frequencies by focusing on satisfying dominant gain-boosting condition and adopting a linear, lossy, and reciprocal-based design approach. Implemented in a 65-nm complementary metal-oxide-semiconductor (CMOS) process, a five-stage dual-band amplifier shows a peak power gain of 23.6 and 13.7 dB, 3 dB bandwidth of 5 and 17 GHz, saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$P_{\text{sat}}$</tex-math></inline-formula> ) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 1.2 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 2.2 dBm, and peak power-added efficiency of 2.1 and 1.5 % at 201 and 283 GHz, respectively, while consuming a dc power of 34.5 mW. The proposed amplifier is the first demonstration of the concurrent dual-band amplifier operating at G- (140–220 GHz) and H- (220–325 GHz) bands.

In this paper, we propose an algorithm with high-reliability for A-Type leakage current detection by applying a Fourier transform. In this study, Fourier transforms were used to improve the reliability of distinguishing between A-type leakage currents and normal currents due to ZCT saturation. The components of each current waveform were analyzed and verified in the frequency domain, and an algorithm using the content of the third harmonic compared to the fundamental was applied. By applying the proposed algorithm, high-reliability were secured compared to the operation of the existing analog A-Type earth leakage circuit breaker.