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161
GIDL analysis of the process variation effect in gate-all-around nanowire FET
Shin-Keun Kim, Youngsoo Seo, Jangkyu Lee, Myounggon Kang, Hyungcheol Shin
Solid-State Electronics, 2017
162
Analysis of metal gate work-function variation for vertical nanoplate FET in 6-T SRAMs
Kyul Ko, Dokyun Son, Myounggon Kang, Hyungcheol Shin
2017
163
Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability
Kyul Ko, Dokyun Son, Myounggon Kang, Hyungcheol Shin
Solid-State Electronics, 2017
164
Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM
Youngsoo Seo, Shin-Keun Kim, Kyul Ko, Changbeom Woo, Min‐Soo Kim, Jangkyu Lee, Myounggon Kang, Hyungcheol Shin
Solid-State Electronics, 2017
165
Analysis on extension region in nanowire FET considering RC delay and electrical characteristics
Jongsu Kim, Changbeom Woo, Myounggon Kang, Hyungcheol Shin
2017
166
Analysis of parasitic capacitance and performance in gate-ail-around and tri-gate channel vertical FET
Youngsoo Seo, Myounggon Kang, Hyungcheol Shin
2017
167
Improvement of dual-Λ spacer for nanowire-FETs considering circuit delay and electricstatic controllability
Hyungwoo Ko, Jongsu Kim, Dokyun Son, Myounggon Kang, Hyungcheol Shin
2017
168
Comparison of parasitic components between LFET and VFET using 3D TCAD
Min‐Soo Kim, Hyungwoo Ko, Myounggon Kang, Hyungcheol Shin
2017
169
Analysis of RC delay for high performance in LFET and VFET
Changbeom Woo, Jongsu Kim, Myounggon Kang, Hyungcheol Shin
2017
170
Analysis of self-heating effects in vertical MOSFETs according to device geometry
Ilho Myeong, Dokyun Son, Hyunsuk Kim, Myounggon Kang, Hyungcheol Shin
2017
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